? 1/7 itaxxb3 bidirectional transil? array for dataline protection rev. 1 so-20 december 2004 main applications differential data transmission lines protection, such as : rs-232 rs-423 rs-422 rs-485 features high surge capability transil array: i pp = 40 a (8/20s) peak pulse power : 300 w (8/20s) separated input - output up to 9 bidirectional transil functions low clamping factor (v cl / v br ) at high current level low leakage current esd protection up to 15kv description transil diode arrays provide high overvoltage protection by clamping action. their instantaneous response to transient overvoltages makes them particularly suited to protect voltage sensitive devices such as mos technology and low voltage supplied ic?s. the ita series combines high surge capability against energetic pulses with high voltage per- formance against esd. the separated input/output configuration of the device ensures improved protection against very fast transient overvoltage like esd by elimination of the spikes induced by parasitic inductances created by external wiring. complies with the following standards: iec61000-4-2 level 4: 15kv (air discharge) 8kv (contact discharge) mil std 883e-method 3015-7: class3 25kv hbm (human body model) table 1: order codes part number marking ita6v5b3 ita6v5b3 ita18b3 ita18b3 ITA18B3RL ita18b3 ita25b3 ita25b3 ita25b3rl ita25b3 asd? figure 1: functional diagram 1 2 3 4 8 7 6 5 20 19 18 17 16 15 14 13 12 11 9 10 gnd gnd gnd gnd input output input output input output input output input output input output input output input output tm: asd and transil are trademarks of stmicroelectronics.
itaxxb3 2/7 table 2: absolute ratings (t amb = 25c) table 3: electrical characteristics (t amb = 25c) symbol parameter value unit p pp peak pulse power (8/20s) (see note 1) t j initial = t amb 300 w i pp peak pulse current (8/20s) (see note 1) t j initial = t amb 40 a i 2 twire i 2 t value (see note 1) 0.6 a 2 s t j maximum operating junction temperature 125 c t stg storage temperature range -55 to +150 c t l maximum lead temperature for soldering during 10 s at 5mm for case 260 c note 1: for surges greater than the specified maximum value, the i/o will first present a short-circuit and after an open circuit cau sed by the wire melting. symbol parameter v rm stand-off voltage v br breakdown voltage v cl clamping voltage i rm leakage current i pp peak pulse current t voltage temperature coefficient v f forward voltage drop c capacitance part number v br @ i r i rm @ v rm v cl @ i pp v cl @ i pp tc min. max. 8/20s max. 8/20s max. max. note 2 note 2 note 2 note 3 vmaavvava 10 -4 /c pf ita6v5b3 6.5 1 10 5 9.5 10 121 25 4 1100 ita18b3 18 1 4 1521102625 9500 ita25b3 25 1 4 243110362512420 note 2: between i/o pin and ground. note 3: between two input pins at 0v bias, f = 1 mhz. v br v cl v rm i rm i pp i v
itaxxb3 3/7 figure 2: pulse waveform figure 3: typical peak pulse power versus exponential pulse duration figure 4: clamping voltage versus peak pulse current (exponential waveform 8/20s) figure 5: peak current i dc inducing open circuit of the wire for one input/output versus pulse duration (typical values) figure 6: junction capacitance versus reverse applied voltage for one input/output (typical values) figure 7: relative variation of leakage current versus junction temperature %i pp t 10s 100 50 0 1000s pulse waveform 10/1000s p pp (w) 1e-03 1e-02 1e-01 1e+00 1e+01 1e+02 1e+01 1e+02 1e+03 1e+04 t j initial=25c t p (ms) expo ita18b3 ita25b3 ita6v5b3 v cl (v) t j initial=25c i pp (a) 1e+00 1e+01 1e+02 1e+03 1e-01 1e+00 1e+01 1e+02 ita18b3 ita25b3 ita6v5b3 %i pp t r 100 50 0 t p t i dc (a) t p (ms) 1e+00 1e+01 1e+02 1e+03 1e-02 1e-01 1e+00 1e+01 exponential waveform c(pf) t j =25c f=1mhz v r (v) 1e+02 1e+03 1e+00 1e+01 1e+02 ita18b3 ita25b3 ita6v5b3 5e+3 1e+3 1e+2 1e+1 0 25 50 75 100 125 150 1e+0 1e-1 t j (c) i r (t ) i (t =25c) j rj v r =v rm
itaxxb3 4/7 this monolithic transil array is based on 610 unidirectional transils with a common cathode and can be configurated to offer up to 9 bidirectional functions. this imposes a maximum differential voltage between 2 input pins (see table 4). table 4: application information figure 8: rs-232 junction (typical application) application notice types maximum differential voltage between two input pins at 25c ita6v5b3 + / - 3.5 v ita18b3 + / - 9.0 v ita25b3 + / - 12.5 v design advantage of itaxxxb3 used with 4- point structure. figure 9: the4-point structure the itaxxxb3 has been designed with a 4-point structure (separated input/output) in order to efficiently protect against disturbances with very high di/dt rates, such as esd. the purpose of this 4-point structure is to eliminate the overvoltage introduced by the parasitic inductances of the wiring (ldi/dt). efficient protection depends not only on the component itself, but also on the circuit layout.the drawing given in figure shows the layout to be used in order to take advantage of the 4-point structure of the itaxxxb3. tx dtr dsr carrier det. aux cts rts rx gnd u chip input 1 di/dt gnd device to be protected gnd output 1
itaxxb3 5/7 figure 10: ordering information scheme figure 11: so-20 package mechanical data figure 12: foot print dimensions (in millimeters) ita 25 b 3 rl integrated transil array breakdown voltage (min) type of lines protected package packaging 25 = 25 volt b = bidirectional 3 = so-20 rl = tape & reel blank = tube eh a a1 b e d k hx45 c l 1.27 0.6 8.5 11.2 ref. dimensions millimeters inches min. typ. max. min. typ. max. a 2.35 2.65 0.092 0.104 a1 0.10 0.20 0.004 0.008 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.6 13.0 0.484 0.512 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.029 l 0.50 1.27 0.020 0.050 k8 (max)
itaxxb3 6/7 table 5: ordering information part number marking package weight base qty delivery mode ita6v5b3 ita6v5b3 so-20 0.55 g 1000 tube ita18b3 ita18b3 1000 tube ITA18B3RL ita18b3 1000 tape & reel ita25b3 ita25b3 1000 tube ita25b3rl ita25b3 1000 tape & reel table 6: revision history date revision description of changes 13-dec-2004 1 first issue.
itaxxb3 7/7 information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered tr ademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com
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